An improved instruction-level power model for ARM11 microprocessor

The power and energy consumed by a chip has become the primary design constraint for embedded systems, which has led to a lot of work in hardware design techniques such as clock gating and power gating. The software can also affect the power usage of a chip, hence good software design can be used to reduce the power further. In this paper we present an instruction-level power model based on an ARM1176JZF-S processor to predict the power of software applications. Our model takes substantially less input data than existing high accuracy models and does not need to consider each instruction individually. We show that the power is related to both the distribution of instruction types and the operations per clock cycle (OPC) of the program. Our model does not need to consider the effect of two adjacent instructions, which saves a lot of calculation and measurements. Pipeline stall effects are also considered by OPC instead of cache miss, because there are a lot of other reasons that can cause the pipeline to stall. The model shows good performance with a maximum estimation error of -8.28\% and an average absolute estimation error is 4.88\% over six benchmarks. Finally, we prove that energy per operation (EPO) decreases with increasing operations per clock cycle, and we confirm the relationship empirically

Modelling Smart Card Security Protocols in SystemC TLM

Smart cards are an example of advanced chip technology. They allow information transfer between the card holder and the system over secure networks, but they contain sensitive data related to both the card holder and the system, that has to be kept private and confidential. The objective of this work is to create an executable model of a smart card system, including the security protocols and transactions, and to examine the strengths and determine the weaknesses by running tests on the model. The security objectives have to be considered during the early stages of systems development and design, an executable model will give the designer the advantage of exploring the vulnerabilities early, and therefore enhancing the system security. The Unified Modeling Language (UML) 2.0 is used to model the smart card security protocol. The executable model is programmed in SystemC with the Transaction Level Modeling (TLM) extensions. The final model was used to examine the effectiveness of a number of authentication mechanisms with different probabilities of failure. In addition, a number of probable attacks on the current security protocol were modeled to examine the vulnerabilities. The executable model shows that the smart card system security protocols and transactions need further improvement to withstand different types of security attacks

Variation Resilient Adaptive Controller for Subthreshold Circuits

Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurately as digital signatures, and an all-digital DC-DC converter incorporating the sensor capable of generating an operating operating Vdd from 0V to 1.2V with a resolution of 18.75mV, suitable for subthreshold circuit operation. The benefits of the proposed controller is reflected with energy improvement of up to 55% compared to when no controller is employed. The detailed implementation and validation of the proposed controller is discussed

Testing of Level Shifters in Multiple Voltage Designs

The use of multiple voltages for different cores is becoming a widely accepted technique for efficient power management. Level shifters are used as interfaces between voltage domains. Through extensive transistor level simulations of resistive open, bridging and resistive short faults, we have classified the testing of level shifters into PASSIVE and ACTIVE modes. We examine if high test coverage can be achieved in the PASSIVE mode. We consider resistive opens and shorts and show that, for testing purposes, consideration of purely digital fault effects is sufficient. Thus conventional digital DfT can be employed to test level shifters. In all cases, we conclude that using sets of single supply voltages for testing is sufficient

General solution of functional equations defined by generic linear-fractional mappings F_1: C^N \to C^N and by generic maps birationally equivalent to F_1

We consider a system of birational functional equations (BFEs) (or finite-difference equations at w=m \in Z) for functions y(w) of the form: y(w+1)=F_n(y(w)), y(w):C \to C^N, n=deg(F_n(y)), F_n \in (\bf Bir}(C^N), where the map F_n is a given birational one of the group of all automorphisms of C^N \to C^N. The relation of the BFEs with ordinary differential equations is discussed. We present a general solution of the above BFEs for n=1,\forall N and of the ones with the map F_n birationally equivalent to F_1: F_n\equiv V\comp F_1\comp V^{-1}, \forall V \in (\bf Bir}(C^N).Comment: 4 pages, 0 figure

Dynamic Voltage Scaling Aware Delay Fault Testing

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

Overview of PUF-based hardware security solutions for the Internet of Things

The Internet of Things (IoT) consists of numerous inter-connected resource-constrained devices such as sensors nodes and actuators, which are linked to the Internet. By 2020 it is anticipated that the IoT paradigm will include approximately 20 billion connected devices. The interconnection of such devices provides the ability to collect a huge amount of data for processing and analysis. A significant portion of the transacted data between IoT devices is private information, which must not in any way be eavesdropped on or tampered with. Security in IoT devices is therefore of paramount importance for further development of the technology. Such devices typically have limited area and energy resources, which makes the use of classic cryptography prohibitively expensive. Physically Unclonable Functions (PUFs) are a class of novel hardware security primitives that promise a paradigm shift in many security applications; their relatively simple architecture can answer many of the security challenges of energy-constrained IoT devices. In this paper, we discuss the design challenges of secure IoT systems; then we explain the principles of PUFs; finally we discuss the outstanding reliability and security problems of PUF technology and outline the open research questions in this field

SRAM-PUF Based on Selective Power-Up and Non-Destructive Scheme

Research in hardware security, particularly on Physical Unclonable Functions (PUF) has attracted a lot of attention in recent years. PUFs provide primitives for implementing encryption/decryption and device fingerprinting. Though a wide range of solutions exists for PUF-based CMOS devices, the most investigated solutions today for weak PUF implementation are based on the use of random start-up values of SRAM, which offers the advantage of reusing memories that already exist in many designs. However, the start-up value availability is compromised during memory write access which causes a limitation in using SRAM as both memory and PUF. Although using a dedicated SRAM as PUF could overcome the problem, it comes with high extra overhead. In this work, we propose a new scheme called ‘selective power-up and non-destructive’ scheme to enable SRAM as memory and PUF. A case study of generating a 128-bit key shows that the area overhead of proposed scheme is approximately 12.5_ smaller than for a dedicated SRAM-PUF